scaffold: OpenScribe open-source self-hosted AI voice recorder
Bootstrap of the project (M0). Sets up the monorepo, design docs, hardware BOM, the open API contract, component skeletons, licensing and CI, following the Default Workflow SOP. What changed: - CLAUDE.md + docs/: copied the Default Workflow so sessions load the SOP. - state/: PROJECT, ARCHITECTURE, DECISIONS, TODO, NOTES filled in for OpenScribe. ARCHITECTURE captures the four-part design (firmware, server, app, case) and the three sync paths; DECISIONS records the hardware, AI-stack, storage, app and licensing choices; TODO lays out milestones M1-M9. - hardware/BOM.md: two build options (compact XIAO ESP32-S3 Sense; dev ESP32-S3 + I2S mic + SD), wiring/pinout, indicative cost. - api/openapi.yaml: the completely open API (device + server surfaces), including recording list/download/delete and exports (wav/ogg/txt/srt/vtt/md/json). - firmware/: PlatformIO ESP32-S3 project, two board profiles, pin map, boot scaffold with module seams for M1-M4. - server/: FastAPI skeleton mirroring the OpenAPI, config for self-hosted MinIO, faster-whisper and Ollama; stub routes browsable at /docs. - app/, case/: Flutter app plan; parametric OpenSCAD enclosure. - Licensing: GPL-3.0 (code), CERN-OHL-S-2.0 (hardware), CC-BY-SA-4.0 (case/docs), REUSE-style LICENSES/ with SPDX headers; LICENSING.md explains the split. - CI: Forgejo Actions workflow builds firmware (both profiles) and lints/imports server. Why: - Everything self-hosted and openly licensed per the user's requirements: an open API, three sync paths (BLE control, WiFi transfer, independent WiFi upload on charge to generic cloud storage), and a full self-hosted transcription+summary stack. Notes: - No custom PCB in v1; off-the-shelf modules. Physical verification waits on parts. - Component code is stubs at M0; features land milestone by milestone, each as its own branch/PR per the workflow. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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firmware/src/main.cpp
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firmware/src/main.cpp
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// SPDX-License-Identifier: GPL-3.0-only
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//
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// OpenScribe firmware entry point.
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//
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// This is the M0 scaffold: it boots, reports the board profile and PSRAM, and defines the
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// module seams the later milestones fill in (see state/TODO.md and state/ARCHITECTURE.md).
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// No audio/WiFi/BLE yet - those land in M1-M4 so each is a reviewable feature branch.
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//
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// Module seams (added incrementally):
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// audio - I2S/PDM mic capture -> PSRAM ring buffer -> WAV encoder (M1)
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// storage - microSD FAT files + sidecar JSON metadata (M1)
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// recorder - record session state machine, file naming (M1)
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// ux - button + LED/haptic (M1)
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// power - battery ADC, charge/VBUS detect -> mode switch (M3)
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// config - NVS settings (WiFi, upload target, codec, token) (M2/M3)
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// net_wifi - WiFi join/reconnect + mDNS (M2)
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// api_http - on-device REST server (api/openapi.yaml device paths) (M2)
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// uploader - S3/WebDAV upload when powered (M3)
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// ble - GATT control + WiFi provisioning (M4)
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// ota - firmware update over HTTP (M9)
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#include <Arduino.h>
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static const char *FIRMWARE_VERSION = "0.1.0-scaffold";
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void setup() {
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Serial.begin(115200);
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delay(300);
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Serial.println();
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Serial.printf("OpenScribe firmware %s booting\n", FIRMWARE_VERSION);
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#if defined(OPENSCRIBE_BOARD_XIAO)
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Serial.println("Board profile: XIAO ESP32-S3 (Build A, PDM mic + onboard SD)");
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#else
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Serial.println("Board profile: ESP32-S3 dev (Build B, I2S mic + SD module)");
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#endif
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if (psramFound()) {
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Serial.printf("PSRAM: %u bytes free\n", (unsigned)ESP.getFreePsram());
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} else {
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Serial.println("WARNING: no PSRAM detected - audio buffering needs a PSRAM board");
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}
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// M1 onwards wires the modules here:
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// config::begin(); storage::begin(); audio::begin(); ux::begin(); ...
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}
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void loop() {
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// Placeholder heartbeat until the recorder state machine lands (M1).
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delay(1000);
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}
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