Laurence
031074c9a9
Bootstrap of the project (M0). Sets up the monorepo, design docs, hardware BOM, the open API contract, component skeletons, licensing and CI, following the Default Workflow SOP. What changed: - CLAUDE.md + docs/: copied the Default Workflow so sessions load the SOP. - state/: PROJECT, ARCHITECTURE, DECISIONS, TODO, NOTES filled in for OpenScribe. ARCHITECTURE captures the four-part design (firmware, server, app, case) and the three sync paths; DECISIONS records the hardware, AI-stack, storage, app and licensing choices; TODO lays out milestones M1-M9. - hardware/BOM.md: two build options (compact XIAO ESP32-S3 Sense; dev ESP32-S3 + I2S mic + SD), wiring/pinout, indicative cost. - api/openapi.yaml: the completely open API (device + server surfaces), including recording list/download/delete and exports (wav/ogg/txt/srt/vtt/md/json). - firmware/: PlatformIO ESP32-S3 project, two board profiles, pin map, boot scaffold with module seams for M1-M4. - server/: FastAPI skeleton mirroring the OpenAPI, config for self-hosted MinIO, faster-whisper and Ollama; stub routes browsable at /docs. - app/, case/: Flutter app plan; parametric OpenSCAD enclosure. - Licensing: GPL-3.0 (code), CERN-OHL-S-2.0 (hardware), CC-BY-SA-4.0 (case/docs), REUSE-style LICENSES/ with SPDX headers; LICENSING.md explains the split. - CI: Forgejo Actions workflow builds firmware (both profiles) and lints/imports server. Why: - Everything self-hosted and openly licensed per the user's requirements: an open API, three sync paths (BLE control, WiFi transfer, independent WiFi upload on charge to generic cloud storage), and a full self-hosted transcription+summary stack. Notes: - No custom PCB in v1; off-the-shelf modules. Physical verification waits on parts. - Component code is stubs at M0; features land milestone by milestone, each as its own branch/PR per the workflow. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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1,010 B
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; SPDX-License-Identifier: GPL-3.0-only
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; OpenScribe firmware - PlatformIO project.
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; Two build profiles: a dev board (Build B) and the compact XIAO ESP32-S3 (Build A).
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; See ../hardware/BOM.md for the matching hardware and pinout.
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[platformio]
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default_envs = esp32s3_dev
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src_dir = src
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include_dir = include
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[env]
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platform = espressif32
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framework = arduino
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monitor_speed = 115200
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build_flags =
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-DCORE_DEBUG_LEVEL=3
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; PSRAM is required for audio ring buffers
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-DBOARD_HAS_PSRAM
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lib_deps =
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; Pinned in later milestones as modules land (I2S mic, SD, BLE, HTTP server).
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; --- Build B: ESP32-S3 dev board with PSRAM (N16R8), external I2S mic + SD ---
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[env:esp32s3_dev]
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board = esp32-s3-devkitc-1
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board_build.arduino.memory_type = qio_opi
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build_flags =
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${env.build_flags}
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-DOPENSCRIBE_BOARD_DEV=1
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; --- Build A: Seeed XIAO ESP32-S3 (Sense) - compact wearable, onboard PDM mic + SD ---
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[env:xiao_esp32s3]
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board = seeed_xiao_esp32s3
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build_flags =
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${env.build_flags}
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-DOPENSCRIBE_BOARD_XIAO=1 |