Laurence
031074c9a9
Bootstrap of the project (M0). Sets up the monorepo, design docs, hardware BOM, the open API contract, component skeletons, licensing and CI, following the Default Workflow SOP. What changed: - CLAUDE.md + docs/: copied the Default Workflow so sessions load the SOP. - state/: PROJECT, ARCHITECTURE, DECISIONS, TODO, NOTES filled in for OpenScribe. ARCHITECTURE captures the four-part design (firmware, server, app, case) and the three sync paths; DECISIONS records the hardware, AI-stack, storage, app and licensing choices; TODO lays out milestones M1-M9. - hardware/BOM.md: two build options (compact XIAO ESP32-S3 Sense; dev ESP32-S3 + I2S mic + SD), wiring/pinout, indicative cost. - api/openapi.yaml: the completely open API (device + server surfaces), including recording list/download/delete and exports (wav/ogg/txt/srt/vtt/md/json). - firmware/: PlatformIO ESP32-S3 project, two board profiles, pin map, boot scaffold with module seams for M1-M4. - server/: FastAPI skeleton mirroring the OpenAPI, config for self-hosted MinIO, faster-whisper and Ollama; stub routes browsable at /docs. - app/, case/: Flutter app plan; parametric OpenSCAD enclosure. - Licensing: GPL-3.0 (code), CERN-OHL-S-2.0 (hardware), CC-BY-SA-4.0 (case/docs), REUSE-style LICENSES/ with SPDX headers; LICENSING.md explains the split. - CI: Forgejo Actions workflow builds firmware (both profiles) and lints/imports server. Why: - Everything self-hosted and openly licensed per the user's requirements: an open API, three sync paths (BLE control, WiFi transfer, independent WiFi upload on charge to generic cloud storage), and a full self-hosted transcription+summary stack. Notes: - No custom PCB in v1; off-the-shelf modules. Physical verification waits on parts. - Component code is stubs at M0; features land milestone by milestone, each as its own branch/PR per the workflow. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
45 lines
2.3 KiB
Markdown
45 lines
2.3 KiB
Markdown
# TODO
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> The current state of play. Keep it honest and current; this is what the next session
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> reads to know what to do. Move items between sections as they progress.
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## In progress
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- [ ] M0 Scaffold - repo, licences, state docs, BOM, OpenAPI, component skeletons, CI
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(branch: bootstrap on `main`; this is the setup commit)
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## Pending (roughly in build order)
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- [ ] M1 Firmware recording core: I2S mic capture -> PSRAM ring buffer -> WAV on microSD,
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button start/stop, LED status, sidecar JSON metadata. (branch `feature/fw-recorder-core`)
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- [ ] M2 On-device WiFi + REST API: WiFi manager, mDNS, list/get/download(range)/delete
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recordings, device status. Implements `api/openapi.yaml` device paths.
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(branch `feature/fw-rest-api`)
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- [ ] M3 Independent uploader: NVS config store, charge/VBUS detect -> powered mode,
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S3-compatible + WebDAV upload of audio + metadata. (branch `feature/fw-uploader`)
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- [ ] M4 BLE GATT: device info, battery, record control, WiFi provisioning, status
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notifications; hand-off to WiFi for transfer. (branch `feature/fw-ble`)
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- [ ] M5 Server ingest + transcription: FastAPI ingest from object store/upload, store,
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faster-whisper transcription, DB, exports (audio/TXT/SRT/VTT/JSON). REST API.
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(branch `feature/server-ingest-stt`)
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- [ ] M6 Server summaries: Ollama LLM summary + action items, Markdown export.
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(branch `feature/server-summary`)
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- [ ] M7 Flutter app: BLE provisioning, device dashboard, library from server API,
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playback, transcript/summary view, export/share, settings.
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(branch `feature/app-mvp`)
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- [ ] M8 3D case: parametric OpenSCAD enclosure fit to the BOM board + battery; print/fit.
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(branch `feature/case-v1`)
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- [ ] M9 Hardening + OTA: API auth, credential handling, OTA update, docs handoff.
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(branch `feature/hardening-ota`)
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## Done
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- [x] Create Forgejo repo `laurence/openscribe` (public, main) - 2026-07-03
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- [x] Decide hardware, sync model, AI stack, app platform, storage, licensing (see
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DECISIONS.md) - 2026-07-03
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## Blocked / waiting
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- [ ] Physical build + on-device verification - waiting on parts from `hardware/BOM.md`.
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Until parts arrive, firmware is developed against the ESP32-S3 target and validated
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by build + (where possible) native/host unit tests, not on real hardware.
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